It is easy to anticipate that it will be necessary to move to a higher number of bits in the quantisation process; both for the professional and the consumer domains. Since a GNSS receiver uses more bits in the sampling process, it resembles a general-purpose DSP with fixed arithmetic. At eight bits, it is questionable whether using silicon to perform GPS correlation offers an actual advantage over using a flexible software implementation on a general-purpose DSP.
The solution proposed uses a low-cost architecture in which a small FPGA is in charge of performing raw signal monitoring and conditioning (e.g. frequency analysis/filtering), to combat in-band power jamming. An embedded CPU runs a software receiver with at least eight bits and addresses more clever techniques of interference (e.g. spoofing/meaconing). Such an instrument should be equipped with a wireless modem to support online updates. It would be an ideal candidate receiver for security-critical applications, but could also function as an interference characterisation tool.